(a) Field of the Invention
The present invention relates to a vertical-cavity surface-emitting semiconductor laser (VCSEL) device and, more particularly, to a VCSEL device having a current-confinement oxide layer.
(b) Description of the Related Art
VCSEL devices are known in the art which emit laser in the direction perpendicular to the main surface of the substrate. The VCSEL devices have an advantage over the conventional semiconductor laser devices having a Fabry-Perot resonator in that a large number of VCSEL devices can be arranged in a two-dimensional array on a common substrate, and thus attract a larger attention these days especially in the field of data communication.
The VCSEL device includes a compound semiconductor substrate such as GaAs or InP substrate, a pair of distributed-Brag-reflector (DBR) mirrors, and a laser resonator sandwiched between the DBR mirrors and including an active layer for lasing at a specific wavelength The DBR mirrors each are configured by a plurality of pairs of semiconductor layers, each pair including a high-refractive-index layer and a low-refractive-index layer. The VCSEL device also includes a current-confinement oxide layer within or adjacent to one of the DBR mirrors, the current-confinement oxide layer including a central current injection area and a peripheral current blocking area which is selectively oxidized from the central current injection area. The current-confinement oxide layer has a current confinement function as well as an optical confinement function to reduce the threshold current required for lasing in the VCSEL device.
In a typical GaAs-group VCSEL device, the DBR mirror formed therein includes a plurality of pairs of AlxGa1−xAs/AlyGa1−yAs layers, wherein x<y. This type of DBR mirror has the advantages of a higher thermal conductivity and a higher reflectance. In addition, GaAs-group VCSEL devices have the advantage of achieving a wider range of lasing frequency as wide as between 600 nm and 1600 nm by modifying the materials of the active layer.
With reference to FIG. 8, the configuration of a conventional VCSEL device will be described hereinafter. FIG. 8 schematically shows the sectional structure of the VCSEL device having a current-confinement oxide layer and lasing at a wavelength of around 850 nm.
The VCSEL device 10 includes an n-type GaAs (n-GaAs) substrate 12, and a layer structure formed thereon and including bottom DBR mirror 14, lower cladding layer 16, quantum-well (QW) active layer 18, upper cladding layer 20, and top DBR mirror 22. The bottom DBR mirror 14 includes 35 pairs of n-Al0.2Ga0.8As/n-Al0.9Ga0.1As layers each having a thickness corresponding to λ/(4n), where λ and n are emission wavelength and refractive index, respectively. The top DBR mirror 22 includes 25 pairs of p-Al0.2Ga0.8As/p-Al0.9Ga0.1As layers each having a thickness corresponding to λ/(4n). The n-Al0.2Ga0.8As layer and p-Al0.2Ga0.8As layer configure the high-refractive-index layer, whereas the n-Al0.9Ga0.1As layer and p-Al0.9Ga0.1As layer configure the low-refractive-index layer.
In the top DBR mirror 22, one of the p-Al0.9Ga0.1As layers near the active layer 18 is replaced by a current-confinement oxide layer 23 configured by an AlAs layer wherein the Al component of the AlAs layer in the peripheral area 25 is oxidized selectively from the central area 24 of the AlAs layer to configure a current blocking area 25 The current-confinement oxide layer 23 has a current confinement function as well as an optical confinement function,
The top DBR mirror 22 is selectively etched using a photolithographic and etching technique to configure a cylindrical mesa post 51E having a diameter of 30 μm, for example, together with the current-confinement oxide layer 23 of the layer structure near the active layer 18.
For manufacturing the conventional VCSEL device 10 as described above, the layer structure configured as the mesa post 51E is subjected to an oxidizing heat treatment at a temperature of 400 degrees C. in a steam atmosphere. The oxidizing heat treatment oxidizes the peripheral annular area 25 of the current-confinement oxide layer 23 while allowing the central area 24 to be non-oxidized. The peripheral current blocking area 25 has a width of 10 μm, for example, and the central area of the current-confinement oxide layer 23 configures a current injection area 24
The mesa post 51E is embedded by a polyimide layer 26 on the periphery or sidewall of the mesa post 51E. The top of the mesa post 51E is attached with an annular p-side electrode 28 having a width of 5 to 10 μm. The bottom surface of the n-GaAs substrate 12 is polished to obtain a thickness of 200 μm for the n-GaAs substrate 12, and an n-side electrode 30 is formed thereon. In addition, a p-side electrode pad 32 in contact with the p-side electrode 28 is formed on the polyimide layer 26
In the conventional VCSEL device 10 as described above, the portion of the layer structure disposed radially outside the mesa post 51E is entirely removed However, another structure is also known in which an annular groove is formed in the layer structure to separate the mesa post 51E from the radially peripheral portion of the layer structure. In this structure, the annular groove is filled with a polyimide layer and the electrode pad is disposed on the peripheral portion of the layer structure.
There is a problem in the conventional VCSEL device 10 that oxidation of the periphery of the AlAs layer does not provide a satisfactory circular shape for the central current injection area 24 in the current-confinement oxide layer 23. The shape actually obtained is roughly a square instead of a circular shape. The current injection area 24 having a square shape or non-circle shape may cause an ununiform electric field in the vicinity of the apexes of the square shape, incurring an electrostatic discharge (ESD) breakdown to thereby degrade the product yield of the VCSEL devices.
A literature “IEEE Journal of selected topics in quantum electronics”, vol. 3, No, 3, 916, 1997 describes a VCSEL device including a current-confinemnent oxide layer configured by Al0.98Ga0.02As instead of AlAs. The Al0.98Ga0.02As layer used as the current-confinement oxide layer 23 has a lower surface orientation dependency of the oxidation rate, thereby achieving a circular shape of the current injection area, which accurately reflects the cylindrical shape of the mesa post.
The accurate circular shape of the current injection area 24 reduces the possibility of the ESD breakdown. However, the Al0.98Ga0.02As layer used for configuring the current-confinement oxide layer 23 incurs a higher restriction on the content ratio of the Al0.98Ga0.02As layer for achieving a current injection area having an improved circular shape. In addition, the Al0.98Ga0.02As layer has a lower oxidation rate compared to the AlAs layer, thereby consuming a larger time length for the oxidation heat treatment. The larger time length incurs oxidation of the periphery of the Al0.9Ga0.1As layer in the DBR mirror, generating a volume reduction of the Al0.9Ga0.01As layer due to the oxidation and degrading the reliability of the VCSEL device.